STMicroelectronics (NYSE: STM), a global semiconductor leader serving customers across the spectrum of electronics applications, today announcednew details regardingthe development of the nextgenerations of Panel-Level Packaging (PLP) technology through a pilot line in its Tours site, France, which is expected to be operational in Q3 2026.
PLP is an advanced, automatedchip packaging and test process technologybringing increased manufacturing efficiency and reducing costs, anda key enabler for creating the next generation of smaller, more powerful, and cost-effective electronic devices. The large-area carrier in PLP (large rectangular shapes in place of circular wafers) enables higher manufacturing throughput, making it a more efficient solution for high-volume production. Building on its first-generation PLP line in operation in Malaysia and its global technology R&D network, ST plans to develop the nextgenerations ofits PLP technology to maintain its technological leadership andextend the use of PLP across many other ST products for automotive, industrial and consumer applications.
“The development of our PLP capabilities in our Tours site is aimed at advancing this innovative approach to chip packaging and test manufacturing technology, boosting efficiency and flexibility so it can be rolled out across a wide portfolio of applications,including RF, analog, power and microcontrollers. Amultidisciplinary team of experts in manufacturing automation, process engineering, data science and analytics, as well as technology and product R&D, will collaborateon this program, which is a key part of a larger strategic initiative focused on heterogeneous integration– a scalable, efficient new approach to chip integration,” said Fabio Gualandris, President Quality, Manufacturing and Technology of STMicroelectronics. “With our fab in Malta, ST has already demonstrated its capability to deliver high-performing chip packaging and test in Europe. As we reshape our global manufacturing footprint, this new initiative in Tours will expand our process, design and manufacturing innovation capabilities supporting the development of next-generation chips in Europe”.
The development of the new PLP pilot line in Tours is supported by a capital investment of over $60 million, already allocated as part of the company-wide program to reshape the Company’s manufacturing footprint.Additional synergies are expected with the local R&D ecosystem, including the CERTEM R&D center. As previously announced, this program is focusedon advanced manufacturing infrastructure and brings redefined missions for some sites in France and Italy to support their long-term success.
Technical note on PLP
For decades, the industry has relied on wafer-level packaging (WLP) and flip-chip technology to connect silicon chips to external circuitry. However, as devices become smaller and more complex, these methods have begun to reach their limits in terms of scalability and cost-effectiveness. For advanced packaging, different approaches exist or are under development; PLP is one of them.
Panel Level Packaging is a method where multiple ICs are packaged on a single, larger rectangular substrate panel, rather than on individual circular wafers. This allows for more ICs to be processed simultaneously, reducing costs and improving throughput.
ST has not only adopted PLP-DCI but has also been at the forefront of its development since 2020. The company’s research and development teams have worked to prototype and scale the technology, culminating in a state-of-the-art PLP-DCI process currently in production at very high volumes of over 5 million units per day on a highly automated line using very large, 700x700mm panels.
ST’s PLP technology focuses on Direct Copper Interconnect (DCI). Direct copper interconnections replace the traditional wire connections of chips with their encapsulation support. DCI is the process by which these ICs are electrically connected to the panel substrate using copper, which is known for its excellent electrical conductivity. DCI offers superior performance compared to traditional methods that use solder bumps, which can be less reliable. This technology with direct connection without wire supports new product development by reducing power losses (such as resistance and inductance), enhancing heat dissipation and enabling miniaturization. This leads to better overall power density.
PLP-DCI also allows the integration of multiple chips within advanced packages, known as System in Package (SiP).
